Speaker
Description
The CASPER philosophy has long championed an open-source, broad scope philosophy with the goal of minimizing time-to-science and engaging as many users in the radio astronomy space as possible. Since CASPER’s inception, this has entailed creating modular, block-based FPGA designs using Simulink and Xilinx System Generator, abstracting away the need for chip-specific and board-specific HDL. Starting in 2020, AMD (Xilinx) released Model Composer, an alternative to System Generator for high-level-synthesis and HDL generation, before completely phasing out System Generator in 2023. This necessitates development of a new front-end for the CASPER toolflow, and presents a crossroads: Either update the toolflow to be compatible with Model Composer or transition to a non-Matlab-based front-end. The latter is appealing because it adheres strongly to the CASPER mission of low-cost, open-source tooling. As such, we have begun developing an alternative front-end for the CASPER toolflow, using Scilab, a free and open-source software package, that still maintains the same modular, block-based design flow as Simulink. In addition to being open-source, Scilab also opens up the possibility of CASPER support for FPGAs from vendors other than Xilinx, such as Altera. Scilab has the added benefit that there are no licensing costs other than for the FPGA vendor's tool. Here-in, I present on initial work to demonstrate the CASPER toolflow on an Altera (Intel) DE10-Nano development board using Scilab as the front-end. I will discuss the steps that needed to be taken to get the CASPER toolflow working as well as future plans for expanding out CASPER support for Altera devices.
